1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device in which a boosted voltage having a high voltage level is generated during low power operation.
2. Description of Related Art
A semiconductor memory device such as a dynamic random access memory (DRAM) has a voltage boosting circuit. The voltage boosting circuit generates a boosted voltage having a higher voltage level than an external power voltage.
The boosted voltage can be used to compensate voltage loss of a transistor and enhance speed of the device. A word line driver circuit, a bit line isolation circuit, and a data output buffer circuit are examples of circuits that use the boosted voltage to compensate voltage loss, and maintain data and high-speed operation.
The voltage boosting circuit is supplied with a cell array internal voltage and a peripheral circuit internal voltage as its power voltage, or operating voltage, to generate the boosted voltage. Typically, the cell array internal voltage and the peripheral circuit internal voltage are lowered implement a low-power semiconductor memory device. A level of the boosted voltage is not substantially lowered due to characteristics of circuits which use the boosted voltage.
The voltage boosting circuit may not be able to generate the boosted voltage when the cell array internal voltage or the peripheral circuit internal voltage has a low voltage level. If the voltage boosting circuit generates the boosted voltage by using the cell array internal voltage or the peripheral circuit internal voltage having a low voltage level, an electric charge pump having an increased size or complicated circuit structure are needed to generate the boosted voltage.
To generate the boosted voltage, the voltage level of the cell array internal voltage or the peripheral circuit internal voltage needs to be maintained at an elevated level, higher than a voltage level that may otherwise be achievable for low-power operation.
The semiconductor memory device additionally employs a voltage boosting circuit power voltage generating circuit, which generates a power voltage of the voltage boosting circuit as shown in FIG. 1.
FIG. 1 is a block diagram illustrating the semiconductor device. The semiconductor memory device of FIG. 1 includes a cell array internal voltage generating circuit 1, a peripheral circuit internal voltage generating circuit 2, a voltage boosting circuit power voltage generating circuit 3, and a voltage boosting circuit 4. The cell array internal voltage generating circuit 1 includes a reference voltage generating circuit 11 and an internal voltage driving circuit 12. The peripheral circuit internal voltage generating circuit 2 includes a reference voltage generating circuit 21 and an internal voltage driving circuit 22. The voltage boosting circuit power voltage generating circuit 3 includes a reference voltage generating circuit 31 and an internal voltage driving circuit 32. The voltage boosting circuit 4 includes a boosted voltage level detecting circuit 41, a control signal generating circuit 42, and an electric charge pump circuit 43.
The semiconductor memory device of FIG. 1 is supplied with one external power voltage VEXT.
The reference voltage generating circuits 11, 21, and 31 are circuits which generate reference voltages REF_A, REF_P, and REF_VPP, respectively, having a constant level regardless of a voltage level of the external power voltage VEXT or an operating temperature of the semiconductor memory device. The reference voltage generating circuit 11 generates a cell array reference voltage REF_A having a prescribed level from the external power voltage VEXT. The reference voltage generating circuit 21 generates a peripheral circuit reference voltage REF_P having a prescribed level from the external power voltage VEXT. The reference voltage generating circuit 31 generates a voltage boosting circuit reference voltage REF_VPP having a prescribed level from the external power voltage VEXT.
The internal voltage driving circuits 12, 22, and 32 are circuits which generate internal voltages VINTA, VINTP, and V_VPP, respectively, according to corresponding reference voltages REF_A, REF_P, and REF_VPP transmitted from the reference voltage generating circuits 11, 21, and 31. The internal voltage driving circuit 12 generates a cell array internal voltage VINTA from the external power voltage VEXT according to the cell array reference voltage REF_A and applies it to the cell array. The internal voltage driving circuit 22 generates a peripheral circuit internal voltage VINTP from the external power voltage VEXT according to the peripheral circuit reference voltage REF_P and applies it to the peripheral circuit. The internal voltage driving circuit 32 generates a voltage boosting circuit power voltage V_VPP from the external power voltage VEXT according to the voltage boosting circuit reference voltage REF_VPP and applies it to the voltage boosting circuit 4.
The boosted voltage level detecting circuit 41 of the voltage boosting circuit 4 detects a voltage level of the boosted voltage VPP and drives the control signal generating circuit 42 when the detected boosted voltage level is lower than the voltage boosting circuit reference voltage REF_VPP. The control signal generating circuit 42 generates a control signal under control of the boosted voltage level detecting circuit 41. The electric charge pump circuit 43 performs charge pumping operation using the voltage boosting circuit power voltage V_VPP in response to the control signal to raise the voltage level of the boosted voltage VPP.
The semiconductor memory device controls the voltage boosting circuit power voltage generating circuit 3 to raise the voltage level of the voltage boosting circuit power voltage V_VPP, thereby generating the boosted voltage VPP having a high voltage level during low-power operation.
In a low-power semiconductor device, the external power voltage of the semiconductor memory device is low, so that the voltage boosting circuit cannot boost the voltage boosting circuit power voltage V_VPP to a desired voltage level.
Therefore, a need exists for a semiconductor memory device in which a boosted voltage having a high voltage level is generated during low power operation.